1. Field of the Invention
The present invention relates to an electronic circuit. More specifically, the present invention relates to a full-wave-rectifier circuit that improves a resolution of on-chip or chip-to-chip capacitance measurements.
2. Related Art
Advances in semiconductor technology presently make it possible to integrate large-scale systems, including tens of millions of transistors, into a single semiconductor chip. Integrating such large-scale systems onto a single semiconductor chip increases the speed at which such systems can operate, because signals between system components do not have to cross chip boundaries, and are not subject to lengthy chip-to-chip propagation delays. Moreover, integrating large-scale systems onto a single semiconductor chip significantly reduces production costs, because fewer semiconductor chips are required to perform a given computational task.
However, these advances in semiconductor technology also pose challenges in intra- and inter-chip communication. Increasing the number of transistors on a single semiconductor chip requires a reduction in the critical dimensions of the transistors and the on-chip signal lines. This reduction in the critical dimensions reduces the capacitances associated with the transistors and on-chip signal lines. These capacitances are critical to chip performance, especially as the chip speed increases. Unfortunately, the reduced capacitances are increasingly difficult to measure. Note that is often necessary to measure these capacitances to calibrate the electronic tools used to design the semiconductor chips and for manufacturing process control purposes.
In addition, the reduction in the critical dimension of the on-chip signal lines is making integration of the semiconductor chips onto a printed circuit board that contains multiple layers of signal lines for inter-chip communication increasingly difficult, since the signal lines on a semiconductor chip are about 100 times more densely packed than signal lines on a printed circuit board.
Researchers have begun to investigate alternative techniques for communicating between semiconductor chips. One promising technique involves integrating arrays of capacitive transmitters and receivers onto semiconductor chips to facilitate inter-chip communication by capacitively coupled communication. Such capacitively coupled communication is highly sensitive to inter-chip alignment, which affects capacitance between the semiconductor chips. In many cases, it is useful to be able to measure capacitance to determine the semiconductor chip alignment. However, the capacitances are small and difficult to measure.
FIG. 1 illustrates an exemplary electronic circuit 100 for measuring capacitance. A signal source 108 produces a square wave signal 110 (shown in FIG. 2) on a node Vtx 112 that transitions between ground and Vdd. A capacitor device under test CDUT 114 couples a charge of Q=CDUT·Vdd or Q=−CDUT·Vdd onto a node Vrx 116 during rising or falling transitions, respectively, of node Vtx 112. Switches S1 118 and S2 120, controlled by Hrect 122 (shown in FIG. 2) and {overscore (Hrect)} 124 (shown in FIG. 2), respectively, connect node Vrx 116 to ground 126 or an ammeter 128.
Capacitors 130 and 132 represent parasitic capacitances due to wiring and device parasitics. Note that capacitors 130 and 132 do not corrupt the capacitance measurement. Rather, capacitors 130 and 132 only slow the signal transitions on nodes Vtx 112 and Vrx 116.
FIG. 2 illustrates signal waveforms as a function of time for electronic circuit 100. The square wave signal 110 on node Vtx 112 couples positive pulses 134 and negative pulses 136 onto node Vrx 116. The positive pulses 134 and negative pulses 136 on Vrx 116 decay as the charge Q on node Vrx 116 is drained through switch S1 118 or S2 120. When Hrect 122 is high, switch S1 118 conducts current and switch S2 120 blocks current. In this case, the ammeter 128 drains the charge Q from the node Vrx 116 and measures a resulting transient current 138. When Hrect 122 is low, switch S1 118 blocks current and switch S2 120 conducts current. Following a negative transition on node Vtx 112, current flows through switch S2 120 to replenish the charge Q removed from node Vrx 116 by the negative transition.
This electronic circuit half-wave rectifies each cycle of charge Q, which is drained through the ammeter 128. For the square wave signal 110 produced by the signal source 108 with a fundamental frequency f, the average current in the ammeter 128 is f·CDUT·Vdd. The capacitance of the capacitor device under test CDUT 114 is determined from the measured average current.
The small capacitances associated with the transistors and on-chip signal lines on semiconductor chips, and the small capacitances between semiconductor chips in capacitively coupled communication, which are discussed above, give rise to small displacement currents. As discussed above, it is increasingly difficult to measure these currents with existing techniques. What is needed is an improved method and an apparatus for measuring capacitance without the problems listed above.